Ministry of
Scientific Research and Information Technology grant (2003-2005)
Hardware implementation of CMOS VLSI
circuit of synchronized oscillators network
for segmentation of binary images
Project head: dr Michal Strzelecki
The objective of this project is to design and
implement CMOS VLSI circuit with the structure of synchronized oscillators
network. This circuit will be used for segmentation of binary images, eg. for
analysis of microscopic skin images. Oscillators network segmentation method is
based on temporary correlation theory, which tries to explain how the scene
analysis is performed by human brain. Computer simulations of oscillator
network proved that it is a reliable tool for segmentation of textured
biomedical images. Project realization will comprise simulation, design,
implementation and testing of network circuit. It will be manufactured by means
of Europractice consortium. Next, the PCI computer card will be designed and
constructed to provide the interface between network chip and PC computer.
Finally, the PC computer equipped with this card will be used for functional
chip testing and segmentation of binary images.
Preliminary simulation
results of oscillator network using SPICE/ICAP4 software by INTUSOFT were presented in:
·
M. Strzelecki, J.
Kowalski, A CMOS oscillator circuit model for image segmentation, Proc. of the I National Conference on
Electronics, Kołobrzeg, Poland, June 10-12, 2002, 253-258 (in Polish)
·
J. Kowalski, M.
Strzelecki, A CMOS circuit design of oscillators network for segmentation of binary
images, Proc. of the II
National Conference on Electronics, Kołobrzeg, Poland, June 9-12, 2003, 169-174
(in Polish)
The network chip was realized as VLSI
CMOS ASIC circuit using AMIS 0.35µm technology by means of Europractice.
Simulation and measurement results of chip functional blocs along with
segmentation of sample binary image were presented in:
·
J. Kowalski, M. Strzelecki, A De Vos, Relaxation
oscillator circuit design for image segmentation, Proc. of IEEE Workshop on Signal Processing 2004,
24 September 2004, Poznan, Poland, pp.
27-31
·
J. Kowalski, M. Strzelecki, Weryfikacja pomiarowa
bloków funkcjonalnych CMOS układu scalonego VLSI sieci oscylatorów do
segmentacji obrazów binarnych, materiały IV Krajowej Konferencji
Elektroniki, 13-15 czerwiec 2005, Darłowo, pp. 519-524 (in Polish)
·
J. Kowalski, M. Strzelecki, CMOS VLSI Chip for
Segmentation of Binary Images, Proc.
of IEEE Workshop on Signal Processing 2005, 30 September 2005, Poznan, Poland,
pp. 251-256
·
J. Kowalski, M.
Strzelecki, P. Majewski, CMOS
VLSI Chip of Network of Synchronised Oscillators: Functional Tests Results, Proc. of IEEE Workshop on Signal
Processing 2006, 29 September 2006, Poznan, Poland, pp. 71-76